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  • dce8c74fa8 Fixed software AES in getResult tevador 2019-02-18 08:45:39 +0100
  • 9a23bdb40d Fixed linux version of SquareHash tevador 2019-02-18 08:44:28 +0100
  • bfd557dac5 Added reference result Fixed undefined initial rounding mode tevador 2019-02-17 10:54:51 +0100
  • 923420f0a3 Fixed mining and verification mode not giving the same results Trace support in Assembly generator tevador 2019-02-16 23:18:45 +0100
  • a145caa185 Fixed JIT compiler not producing the same code as genAsm and genNative tevador 2019-02-15 16:43:52 +0100
  • f0d52fcf4d Fixed dependent constants tevador 2019-02-15 11:38:20 +0100
  • ff0c5a58b3 More compact bytecode tevador 2019-02-15 11:14:40 +0100
  • 447e8a1d4f Simplified division in interpreted mode Fixed incorrect condition code in JitCompilerX86 Refactoring tevador 2019-02-15 10:41:02 +0100
  • 1df975e583 Restored software AES support tevador 2019-02-13 22:46:32 +0100
  • f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult tevador 2019-02-13 00:01:34 +0100
  • 376c868ca0 Fixed wrong REX prefix in FDIV_M code tevador 2019-02-12 23:20:10 +0100
  • 5a89c9b28e Use allocExecutableMemory tevador 2019-02-12 18:18:02 +0100
  • 0b1761a846 Refactoring: mining/verification mode tevador 2019-02-11 18:57:42 +0100
  • 69764966c0 Position independent loads fixed #21 tevador 2019-02-11 18:13:03 +0100
  • 49581e503a
         Merge pull request #20 from antanst/fix-uname tevador 2019-02-11 16:00:17 +0100
  • dd2c894d69 Use portable uname flag, handle OpenBSD case of amd64 Antonis Anastasiadis 2019-02-11 16:51:34 +0200
  • e54697b952
         Correct hashrate of i7-8550U with large pages tevador 2019-02-10 00:20:21 +0100
  • 98c4ccf5ca Merge branch 'dev' tevador 2019-02-09 20:02:14 +0100
  • 85b31342e1 Removed old documentation tevador 2019-02-09 20:02:08 +0100
  • b8ce504be6 Added comments to hashAes1Rx4 and fillAes1Rx4 Fixed gcc compilation Added performance numbers tevador 2019-02-09 19:32:53 +0100
  • 2798d78717 Render imm32 as signed in RandomX code tevador 2019-02-09 16:19:15 +0100
  • 9af0cbf108 Documentation formatting tevador 2019-02-09 16:09:55 +0100
  • 32d827d0a6 Interpreter with bytecode Fixed some undefined behavior with signed types Fixed different results on big endian systems Removed unused code files Restored FNEG_R instructions Updated documentation tevador 2019-02-09 15:45:26 +0100
  • a586751f6b Removed FPNEG instruction Optimized instruction frequencies Increased the range for A registers from [1,65536) to [1, 4294967296) tevador 2019-02-07 16:11:27 +0100
  • ac4462ad42 Renamed floating point instructions Fixed negative source operand for FMUL_M and FDIV_M tevador 2019-02-05 23:43:57 +0100
  • b417fd08ea 16 -> 8 chained programs constant address loads are always from L3 tevador 2019-02-05 23:06:44 +0100
  • 1ee94bef2a Added ISWAP instruction Scratchpad -> 2 MiB New scratchpad initialization New dataset initialization tevador 2019-02-04 17:07:00 +0100
  • ab859879a2
         loop body = 128 instructions tevador 2019-01-27 20:10:03 +0100
  • 20eb549725 Merged load/store of integer and FP registers tevador 2019-01-27 19:33:55 +0100
  • 8f2abd6c05 NOP instruction register load/store from L3 tevador 2019-01-27 18:19:49 +0100
  • 005c67f64c Added explicit STORE instructions JIT compiler tevador 2019-01-27 10:52:30 +0100
  • 7c049cce8d
         Added store instructions tevador 2019-01-24 21:49:39 +0100
  • 5b7df0c5e1
         Test ASM for a new program structure tevador 2019-01-24 19:35:11 +0100
  • d2cb086221 ASM code generator for "small" programs that fit into the uOP cache tevador 2019-01-24 19:29:59 +0100
  • bd0dba88a8 4 scratchpad segments tevador 2019-01-20 00:44:01 +0100
  • 16db607025 Scratchpad size increased to 1 MiB New AES-based scratchpad hashing function tevador 2019-01-18 23:51:18 +0100
  • 93c324709b Related to previous changes tevador 2019-01-18 19:06:46 +0100
  • 89bc68d093 Memory-bound dataset initialization tevador 2019-01-18 18:44:06 +0100
  • 4fb168e249 Large page support for cache Bug fixes tevador 2019-01-18 17:57:47 +0100
  • 8b1102ee05 Interpreter + async mode tevador 2019-01-15 00:01:11 +0100
  • c2e0122e15
         Comparison with CryptoNight tevador 2019-01-13 23:51:12 +0100
  • a7ffe8c19a Mix dataset cacheline with registers r0-r7 tevador 2019-01-13 21:14:59 +0100
  • 48d85643de Dataset intialization algorithm (AES) tevador 2019-01-13 13:47:25 +0100
  • 67e741ff22 Reduced x86 code size by 512 bytes (and ecx -> and eax) tevador 2019-01-12 20:27:35 +0100
  • 1426fcbab5 Print average program code size Fixed assembly for MUL_64 and IMUL_32 Division weight 4 -> 8 tevador 2019-01-12 16:05:09 +0100
  • 2756bcdcfe Added magic division to JIT compiler New B operand selection rules tevador 2019-01-11 16:53:52 +0100
  • 451dfc5730 Optimized division by constants tevador 2019-01-11 14:08:21 +0100
  • c02ee4291d FPROUND - variable flag offset tevador 2019-01-11 10:52:12 +0100
  • e487092f07 Simplified CALL and RET tevador 2019-01-11 10:18:24 +0100
  • 557241cd95 JUMP instruction tevador 2019-01-11 09:58:06 +0100
  • 6941b2cb69 Reworked instruction set documentation tevador 2019-01-10 23:36:53 +0100
  • d1a808643d Random accesses - JIT compiler tevador 2019-01-10 22:04:55 +0100
  • b71e0eec65 Optimizations to reduce code size under 32K tevador 2019-01-08 14:50:31 +0100
  • b6d654291f 90 address transformations tevador 2019-01-08 12:19:19 +0100
  • 2f6a599ff6 Inlined calls for memory read tevador 2019-01-07 17:44:43 +0100
  • 6519fed4d1 Combined prefetch + read into a single step tevador 2019-01-06 21:26:53 +0100
  • 4189e4ebc6 Original number of VM instructions tevador 2019-01-06 17:23:05 +0100
  • 619bee5418 Random dataset accesses - asm only Initial support for large pages tevador 2019-01-04 19:44:15 +0100
  • bf8397b08d Updated specification tevador 2018-12-31 19:27:31 +0100
  • 3caecc7646 Vector FPU instructions JitCompilerX86 - static code written in asm Updated ALU/FPU tests Updated instruction weights tevador 2018-12-31 19:06:45 +0100
  • a09bee8d60 js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up) tevador 2018-12-28 14:18:41 +0100
  • 76b6b05cf2 Unconditional RET tevador 2018-12-28 12:09:37 +0100
  • 39c569ae44 Fixed a potential crash in JitCompilerX86 tevador 2018-12-27 21:42:38 +0100
  • 5bc26348f1 Updated readme with performance data Added --help option tevador 2018-12-23 18:02:17 +0100
  • 03913d0e81 Run a single thread synchronously tevador 2018-12-23 15:12:54 +0100
  • c05947db09 Bug fixes tevador 2018-12-23 14:25:22 +0100
  • ca59925495 JitCompilerX86: use mmap to allocate an executable buffer compile as c++11 tevador 2018-12-23 14:09:09 +0100
  • 740c40b218 8 branch conditions for CALL/RET tevador 2018-12-21 22:41:35 +0100
  • 55afe9646f Debuggable assembly generator tevador 2018-12-21 21:09:55 +0100
  • fce6e75689 Fixed copyright notice tevador 2018-12-21 21:04:35 +0100
  • ffa67295c4 Instruction statistics tevador 2018-12-20 22:42:47 +0100
  • 1db7dd6e8b Renamed immediate constants tevador 2018-12-20 18:36:09 +0100
  • b9d2d853aa Support for multiple threads tevador 2018-12-19 21:54:44 +0100
  • cb12feaf91 t1ha2 hash for scratchpad digest tevador 2018-12-19 12:38:10 +0100
  • ed0bc906d6 JIT compiler for x86 tevador 2018-12-18 22:00:58 +0100
  • ddc29cb4d3 Optimized x86 initialization tevador 2018-12-16 15:10:03 +0100
  • 4f276541d2 Modified x86 register allocation tevador 2018-12-16 13:43:18 +0100
  • 6332831ec1 Implemented cache shift Fixed assembly code generator Fixed an error in the interpreter Updated specification: sign-extended immediates tevador 2018-12-15 23:13:17 +0100
  • 4fc4b840f5 Updated documentation tevador 2018-12-14 12:12:18 +0100
  • d6ca408ce2 Merge branch 'master' of git@github.com:tevador/RandomX.git tevador 2018-12-13 23:16:04 +0100
  • cb0721056a Assembly code generator for Windows 64-bit tevador 2018-12-13 23:11:55 +0100
  • 52beccc309
         Merge pull request #6 from vielmetti/patch-1 tevador 2018-12-12 16:46:39 +0100
  • 8ef8224270
         update ifdef for _rotr on aarch64 Edward Vielmetti 2018-12-12 07:54:33 -0500
  • c9102ee88c RandomX portable interpreter tevador 2018-12-11 21:00:30 +0100
  • 072130c774 ALU/FPU test: Fixed MSVC x86 build tevador 2018-11-20 22:41:34 +0100
  • f19995d4c5 ALU and FPU tests tevador 2018-11-19 22:53:19 +0100
  • ec2d378fce Updated specification tevador 2018-11-18 11:38:33 +0100
  • 7e582c2815
         Updated specification and instruction weights tevador 2018-11-16 19:30:38 +0100
  • 1cc4fda4e7 Improved DRAM random access address space tevador 2018-11-16 19:05:18 +0100
  • d3739015ea Fixed random read frequency tevador 2018-11-16 18:12:32 +0100
  • 9ed71ae167 New DRAM reading pattern New instruction weights tevador 2018-11-16 16:35:17 +0100
  • 58ae98c6a4 Fixed clang compilation tevador 2018-11-14 22:41:51 +0100
  • df9180a30b Performance benchmark for x86 tevador 2018-11-14 20:17:44 +0100
  • 1ca1046c57 Fixed unaligned memory errors tevador 2018-11-11 18:22:52 +0100
  • 71bf9bd096 Fixed a possible type error in python tevador 2018-11-11 13:59:17 +0100
  • 8e565a4ce2 Merge branch 'master' of git@github.com:tevador/RandomX.git tevador 2018-11-11 13:05:50 +0100
  • 8f3b145fe6 Added DRAM buffer option to rx2c tevador 2018-11-11 13:05:34 +0100
  • e018624f87
         Table formatting tevador 2018-11-10 22:35:24 +0100
  • 2ea440d0f5 New instruction encoding tevador 2018-11-10 22:25:51 +0100
  • 3b2cb9b8c7 Merge branch 'master' of git@github.com:tevador/RandomX.git tevador 2018-11-09 21:06:59 +0100